Jan 2026 - Present
VLSI Digital Intern
Samsung Semiconductor India Research (SSIR)
About Me
I’m currently pursuing my M.Tech in ECE at IIIT Bangalore. I completed my B.Tech in Electrical and Electronics Engineering from Amrita Vishwa Vidyapeetham. My academic background helped me build a clear understanding of digital design and VLSI fundamentals.
My focus areas include physical design and static timing analysis. I’ve started my internship at Samsung Semiconductor India Research (SSIR), where I’m getting exposure to real design flows and industry practices.
Technical Skills
Languages
Verilog
Python
C
TCL
EDA Tools
Cadence Virtuoso
Cadence Genus
Cadence Innovus
OpenLANE
OpenSTA
OpenROAD
Xilinx Vivado
MATLAB
LTspice
KiCAD
Technologies
Linux
Git
Relevant Coursework
Digital CMOS VLSI
VLSI Architecture
Digital Electronics
System Design with FPGA
Embedded Systems
ASIC Design
Experience & Education
2024 - 2026
Master of Technology in ECE
International Institute of Information Technology, Bangalore
CGPA: 3.06/4.0
Specialization in VLSI
2017 - 2021
Bachelor of Technology in EEE
Amrita Vishwa Vidyapeetham
CGPA: 9.01/10.0
First Class with Distinction
Projects
Physical Design of RISC-V Core Using OpenLane
Implemented the complete RTL-to-GDSII flow for the PicoRV32a RISC-V core. Performed STA, DRC, and LVS verification, generating the final GDSII file using Magic and KLayout for fabrication readiness.
OpenLane
OpenROAD
RTL-to-GDSII
STA
Low-Power Dual-Edge Triggered Flip-Flop
Engineered a novel Low-Power Redundant-Transition-Free TSPC DET Flip-Flop in 45nm GPDK, achieving a 15% reduction in power consumption and the best Power-Delay Product (PDP) among tested circuits.
Cadence Virtuoso
Low-Power Design
Approximate and Iterative Posit Multiplier
Designed and implemented an Approximate and Iterative Posit Multiplier on a Basys 3 FPGA. Developed key components like decoder, mantissa multiplier, and encoder. Implemented in Python for error analysis.
Verilog
Xilinx Vivado
FPGA
Python
Performance Analysis of Full Adder
Designed and implemented Full Adders at the transistor level using 45nm and 90nm CMOS nodes. Performed comparative analysis of delay and power consumption to evaluate the impact of technology scaling.
Cadence Virtuoso
CMOS
45nm
90nm
I2C Bootloader Implementation
Developed and integrated an I2C Bootloader for the PSoC 5LP microcontroller using PSoC Creator. Configured the bootloader host and successfully implemented I2C communication for firmware upgrades.
C
PSoC 5LP
I2C
Bootloader
PCB Design of Wireless Power Bank
Designed a complete PCB for a 10000 mAh wireless power bank supporting USB PD 3.0 and Qi standards. The design includes a boost converter, battery management system, and wireless transmitter IC.
KiCAD
PCB Design
Wireless Charging
Publications
Performance analysis of Hexapod leg with different controllers
Conference: 12th IEEE International Conference on Communication and Electronics Systems (ICCES), Aug 2021.
Writings
Keep an eye here. I will be adding more blogs and articles about VLSI concepts, sharing insights from my industry experience in the future.
Get In Touch
I’m currently gaining industry experience in VLSI design. If you have questions or would like to connect, feel free to reach out.