Likithkumar Rachaputi

VLSI Engineer

M.Tech @ IIIT Bangalore

Designing the Future of Semiconductor Technology

A motivated Master's student at the International Institute of Information Technology, Bangalore, specializing in Digital VLSI design. Possess hands-on experience in the complete RTL-to-GDSII flow. Proficient with industry-standard EDA tools including the Cadence suite and languages such as Verilog, C, and Python.

Technical Skills

Languages

Verilog SystemVerilog Python C TCL

EDA Tools

Cadence Virtuoso Cadence Genus Cadence Innovus OpenLANE OpenSTA OpenROAD Xilinx Vivado MATLAB LTspice KiCAD

Technologies

Linux Git Docker

Relevant Coursework

Digital CMOS VLSI VLSI Architecture Digital Electronics System Design with FPGA Embedded Systems ASIC Design

Education

Master of Technology in ECE

International Institute of Information Technology, Bangalore

2024 - 2026

CGPA: 3.06/4.0

Specialization in VLSI

Bachelor of Technology in EEE

Amrita Vishwa Vidyapeetham

2017 - 2021

CGPA: 9.01/10.0

First Class with Distinction

Projects

Physical Design of RISC-V Core Using OpenLane

Implemented the complete RTL-to-GDSII flow for the PicoRV32a RISC-V core. Performed STA, DRC, and LVS verification, generating the final GDSII file using Magic and KLayout for fabrication readiness.

OpenLane OpenROAD RTL-to-GDSII STA

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Low-Power Dual-Edge Triggered Flip-Flop

Engineered a novel Low-Power Redundant-Transition-Free TSPC DET Flip-Flop in 45nm GPDK. Achieved the lowest power consumption and best PDP among tested circuits.

Cadence Virtuoso Low-Power Design

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Approximate and Iterative Posit Multiplier

Designed and implemented an Approximate and Iterative Posit Multiplier on a Basys 3 FPGA. Developed key components like decoder, mantissa multiplier, and encoder. Implemented in Python for error analysis.

Verilog Xilinx Vivado FPGA Python

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Performance Analysis of Full Adder

Designed and implemented Full Adders at the transistor level using 45nm and 90nm CMOS nodes. Performed comparative analysis of delay and power consumption to evaluate the impact of technology scaling.

Cadence Virtuoso CMOS 45nm 90nm

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I2C Bootloader Implementation

Developed and integrated an I2C Bootloader for the PSoC 5LP microcontroller using PSoC Creator. Configured the bootloader host and successfully implemented I2C communication for firmware upgrades.

C PSoC 5LP I2C Bootloader

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PCB Design of Wireless Power Bank

Designed a complete PCB for a 10000 mAh wireless power bank supporting USB PD 3.0 and Qi standards. The design includes a boost converter, battery management system, and wireless transmitter IC.

KiCAD PCB Design Wireless Charging

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Publications

Performance analysis of Hexapod leg with different controllers

Conference: 12th IEEE International Conference on Communication and Electronics Systems (ICCES), Aug 2021.

View on IEEE Xplore

Get In Touch

I'm actively seeking internship and full-time opportunities in VLSI design and verification. If you have any questions or would like to discuss potential collaborations, please feel free to reach out.